Título (Bold 12)

The advantages of fully-depleted (FD) SOI CMOS technology in comparison to bulk Si regarding analogue circuit design have been reported in [1]. Most of them relate to the combination of the reduced capacitance of SOI technology with the better transconductance (gm) over drain current (IDS) ratio due to the reduced FD body factor, which provides enhanced bandwidth and gain, resulting in very significantly improved micropower CMOS amplifiers. However, FD devices suffer from output impedance degradation due to the low drain breakdown [2]. One of the most important building blocks for analogue circuit operation is the current-mirror (CM), which drives current for the several circuit branches. Ideal CM operation presupposes to deliver an output current (IOUT) similar to the input current (IIN), independently of the output transistor drain bias (VDSout), i. e. the ratio R=IOUT/IIN closer to unity. Due to the output impedance reduction, the performance of CM made using FD devices is significantly degraded, mainly in moderate and weak inversion regimes, which is of importance to increase the output swing in low voltage operation. The Graded-Channel SOI MOSFET (GC) is an asymmetric channel device which has been introduced recently with the aim to reduce the inherent parasitic bipolar effects of SOI devices (Fig. 1) [3]. GC transistors indeed demonstrated significantly enhanced drain breakdown voltage, superior transconductance in saturation and significantly reduced drain output conductance [4]. In a first approximation, the device effective channel length is equal to L-LLD [3].